A crystal's load capacitors

A crystal does not oscillate “in mid-air”: it oscillates at its nominal frequency only when it sees a precise capacitance at its terminals — the datasheet load capacitance CL. You provide that capacitance, with two external capacitors. Getting them wrong is the most common and silent mistake in clock design: the oscillator still starts, but off frequency. This tool sizes them; this page explains how and why.

What load capacitance is

The load capacitance (CL) is the capacitance the crystal must “feel” between its two pins to resonate at the frequency printed on the label. It is a property of the crystal, not a free value: a 12 pF and an 18 pF crystal, at the same nominal frequency, need different load networks. Typical values lie between 8 and 20 pF.

That capacitance is not inside the crystal: you supply it externally, with two capacitors (one per branch, to ground) in the typical Pierce topology used by almost every microcontroller.

Why two capacitors, and the formula

The two external capacitors C1 and C2 are, from the crystal’s point of view, in series (their common node is AC ground). To that series the stray capacitance of traces and pins is added. The load capacitance seen by the crystal is therefore:

$$C_L=\frac{C_1{C}_2}{C_1+C_2}+C_{\text{stray}}$$

In the usual case of equal capacitors (C1 = C2 = C) the series equals C/2, and the formula simplifies:

$$C_L=\frac{C}{2}+C_{\text{stray}}\Rightarrow C_1=C_2=2(C_L-C_{\text{stray}})$$

Example: a crystal with CL = 12 pF on a layout with C_stray ≈ 3 pF (lumped value) needs C1 = C2 = 2·(12 − 3) = 18 pF. If you ignore the stray and fit 24 pF “because 12·2”, the effective load becomes 24/2 + 3 = 15 pF instead of 12: the crystal runs with +3 pF of load and the frequency shifts.

Typical values (C_stray ≈ 3 pF lumped)

The table holds only for that stray value: change the layout (or the MCU package) and the numbers move. This is why there is no “universal 22 pF cap” — the right value depends on your crystal’s CL and your PCB.

Estimating C_stray

The per-branch stray capacitance sums two contributions:

• PCB traces between capacitor, crystal and chip pin: keep them short and symmetric, with a grounded guard ring under the crystal. Typically 1–3 pF.
• Package pin (OSC_IN / OSC_OUT): often given in the MCU datasheet as the oscillator-pin capacitance. Typically 1–3 pF.

With no precise data, 2–5 pF is a reasonable estimate for a careful layout. The tool has a separate field for the MCU-pin contribution, if you want to keep it distinct from the PCB one: the two are summed.

Careful: lumped, not per branch

There is a semantic trap here worth a few pF, that is tens of ppm. In the application-note formula C_stray is a stray capacitance lumped across the crystal terminals, added to CL just once. A genuinely per-branch stray to ground — the capacitance of a single trace, the one you measure or simulate — sits instead in parallel with C1 and with C2, and then the series becomes:

$$\frac{(C+C_b)(C+C_b)}{2(C+C_b)}=\frac{C}{2}+\frac{C_b}{2}$$

that is, it contributes half. If you measure 3 pF on each trace and type that as C_stray, you ask the calculation for 3 pF of correction where 1.5 pF is needed: the capacitors come out 3 pF smaller and the effective CL 1.5 pF lower, which at 11 ppm/pF is 16 ppm in the wrong direction. The rule that keeps you out of trouble: the field takes (pin-to-pin coupling) + (per-branch stray)/2, and the typical 2–5 pF of the application notes is already expressed in that form.

What getting it wrong costs: pulling, computed

If the effective load capacitance departs from CL, the crystal frequency shifts — the phenomenon is called pulling. The sensitivity in ppm/pF is often tabulated in the datasheet, but there is no need to take it on trust: it follows from the two equivalent-circuit parameters every datasheet gives, the static capacitance C₀ (a few pF, in parallel with the motional branch) and the motional capacitance C_m (a few femtofarad). The loaded resonance frequency and its derivative are:

$$f_L=f_s\left[1+\frac{C_m}{2(C_0+C_L)}\right]⟹S=\frac{\mathrm{d}f/f}{\mathrm{d}{C}_L}=-\frac{C_m}{2(C_0+C_L{)}^2}$$

Two readings. First: the sensitivity sits between 3 and 45 ppm/pF, so one pF of error already costs more than the typical tolerance of a timekeeping crystal (±20 ppm). Second, less obvious: the sensitivity goes as 1/(C₀ + CL)², that is a low-CL crystal is far twitchier. Between CL = 8 and CL = 20 pF the factor is about 4: the same layout error, on the same PCB, moves the frequency four times as much. This is why 6–8 pF crystals demand a much more disciplined layout than 18–20 pF ones, and not the other way round as the “less capacitance = fewer problems” intuition would suggest.

The hierarchy of errors

Lined up, the contributions to the CL error carry very different weight — and the one people tend to think about (E-series rounding) is not the first:

First place goes to the stray estimate, which is also the only entry that cannot be checked after the fact without instruments. That flips the practical priority: first take care of the layout (short symmetric traces, a ground guard ring, nothing else under the crystal) and look up the pin capacitance in the MCU datasheet; then it makes sense to argue about 18 pF versus 20 pF, and only last about 2 % versus 5 % tolerance.

And in time, how much is that

For a 32.768 kHz RTC — the case where pulling is visible to the naked eye — ppm translate like this:

One single pF of load error on an 11 ppm/pF crystal is therefore worth about a second a day: a clock that loses half a minute a month with nothing “broken” anywhere.

The consequences:

• Drifting timing. An RTC off by 20 ppm accumulates about 1.7 seconds per day. In a UART or a bus the clock error adds to the baud error and can drop frames.
• Interoperability. Protocols with tight clock tolerances (USB, Ethernet, CAN) may fall outside the allowed window.
• EMC. An off-frequency clock moves the spectral lines of the emissions; in an electromagnetic-compatibility test a line that moves may land where one used to pass, or vice versa. A badly loaded oscillator is a silent way to fail a pre-compliance run.

Choosing E-series values

Capacitors only come in standard values (E-series): E12 has 12 values per decade (10% tolerance), E24 has 24 (5%). The computed ideal value almost never matches a standard one, so you pick the nearest and check the resulting error on the effective CL. The tool shows both the nearest E12 and E24 values, and computes the effective CL on E24 — the finer series, the one you would use for a precision capacitor.

One case deserves a note: CL = 10 pF asks for 14 pF, which does not exist in E24 (between 13 and 15, equidistant). The value picked is 13 pF and the effective CL drops to 9.5 pF, −5 %: the worst row in the table. With 15 pF it would go to 10.5 pF, +5 %, symmetric — and in that case the choice is made on the sign, not the magnitude, because it is preferable to sit above the nominal CL (more load → lower frequency, a more comfortable oscillation margin) than below it.

In order of magnitude, though, rounding is not the problem: the worst row in the table is worth 8 ppm, less than the tolerance of the capacitor itself.

When the computed value is of no use

There is a region where the formula returns a positive number you cannot use. Below 4 pF the typical uncertainty on the stray (±1 pF) is a quarter of the value: the effective CL depends more on the layout than on the component, and the design does not repeat from one board to the next. The tool flags this without hiding the result — it is not a specification limit, it is a reproducibility threshold.

The 6 pF stray column is why a CL = 6 pF crystal has to be chosen together with the layout and not after it: on a mediocre PCB no capacitor exists that will make it run on frequency.

Limitations

• The model assumes the two capacitors are equal (C1 = C2), the standard case of a crystal Pierce oscillator.
• It sizes the load capacitance only: it does not assess the drive level, the crystal ESR, the oscillator negative resistance or the oscillation margin — checks that need the crystal parameters and sometimes a measurement. The two are linked, though: the load capacitors sit in the feedback path, so raising them lowers the loop gain and tightens the oscillation margin, while the power dissipated in the crystal grows with the square of CL, P = ESR·(2πf·C_L·V_rms)²:

With a typical maximum of 100 µW for a small SMD part, the 72.8 µW row is already close to the limit: overdriving a crystal does not just push it off frequency, it ages it. The classic oscillation-margin criterion — oscillator negative resistance at least 5 times the crystal’s maximum ESR — has to be checked separately, and on high-ESR crystals (32.768 kHz, typically tens of kΩ) it is often the constraint that decides, not the CL.

• The pulling in ppm is not computed by the tool, because it needs the crystal’s C₀ and C_m as user input: the sensitivity section shows how to work it out by hand from the datasheet.
• Drive level and oscillation margin are not evaluated: those are checks on the amplifier, not on the load network.

References

• Vendor application notes — both microcontroller and crystal vendors publish application notes on Pierce oscillator design, load-capacitance selection and oscillation-margin calculation. They are the operational reference for the real case.
• Related tool — the load-capacitor calculator puts this page into practice: enter CL and stray capacitances and get the two caps, the E-series value and the error.