Crystal Load Cap

How is it computed?

A crystal oscillates at its nominal frequency only if it “sees” the datasheet load capacitance CL: the series of the two external capacitors plus the lumped PCB and pin stray. With C1 = C2 this gives CL = C/2 + C_stray, so C1 = C2 = 2·(CL − C_stray). The tool computes the ideal value, rounds it to the nearest E12/E24 and recomputes the effective CL with its error.

A crystal oscillates at its nominal frequency only if it "sees" the load capacitance CL given by the datasheet. That capacitance is the series of the two external capacitors plus the PCB+pin stray, per branch:

$$\begin{array}{rcl}{C}_L& =& \frac{C_1{C}_2}{C_1+C_2}+C_{\text{stray}}\\ \text{con }{C}_1=C_2=C\Rightarrow C_L& =& \frac{C}{2}+C_{\text{stray}}\\ \Rightarrow C_1=C_2& =& 2(C_L-C_{\text{stray}})\end{array}$$

The tool computes the ideal value, rounds it to the nearest E12/E24 value (capacitors come in standard values) and recomputes the effective CL with the resulting error.

Why does the load capacitance matter?

If the effective load capacitance departs from CL, the crystal frequency shifts (pulling) by several ppm. It is the most common and silent mistake: the clock seems to run but is off frequency, and in a communication system the ppm build-up breaks timing. An off-frequency clock can also move the emissions and fail EMC tests.

If the effective load capacitance departs from CL, the crystal frequency shifts (pulling) by several ppm. It is the most common and silent mistake: the clock seems to run but is off frequency, and in a communication system the ppm build-up breaks timing. An off-frequency clock can also move the emissions and fail EMC tests.

Estimating C_stray

The per-branch stray sums two contributions: the PCB traces between caps, crystal and pins (keep them short and symmetric, typically 1–3 pF) and the package-pin capacitance (OSC_IN/OSC_OUT, from the MCU datasheet, typically 1–3 pF). With no data, 2–5 pF per branch is a reasonable estimate; the MCU-pin field lets you keep the chip contribution separate.

What are the E12 / E24 series?

Capacitors only come in standard (E-series) values: E12 with 12 values per decade (10% tolerance), E24 with 24 values (5%). The tool shows the nearest of both; the effective CL and error are computed on E24, the finer one. On a tie the lower value is chosen.

Capacitors only come in standard (E-series) values: E12 with 12 values per decade (10% tolerance), E24 with 24 values (5%). The tool shows the nearest of both; the effective CL and error are computed on E24, the finer one. On a tie the lower value is chosen.

What are the tool’s limitations?

The tool assumes the two capacitors equal (C1 = C2), the standard case for a crystal Pierce oscillator, and sizes the load capacitance only: it does not assess drive level, ESR, negative resistance or oscillation margin. The ppm frequency pulling depends on the crystal sensitivity (ppm/pF) and is not estimated. Demonstrative tool: real design relies on the crystal and MCU datasheets.

• It assumes the two capacitors are equal (C1 = C2), the standard case for a crystal Pierce oscillator.
• It sizes the load capacitance only: it does not assess drive level, ESR, negative resistance or oscillation margin (these need the crystal and package parameters).
• The frequency pulling in ppm depends on the crystal sensitivity (ppm/pF, from the datasheet) and is not estimated here.
• Demonstrative tool: real oscillator design relies on the crystal and MCU datasheets.

References

• Generic application notes on crystal (Pierce) oscillator design and load capacitance, published by MCU and crystal vendors.

Learn more: crystal load capacitance wiki →