UART Baud Error
Check a UART configuration: from the peripheral clock and the desired baud get the divisor, actual baud and percentage error, and see at a glance which standard bauds are "clean" at that clock. Demonstrative tool.
1 · Peripheral
2 · UART configuration
Result
baud = f_periph / (oversampling · divisor). Thresholds for one end (3.95% combined budget): |err| < 2% ok, 2–3% borderline, > 3% drops frames. Demonstrative tool.
Standard bauds at this clock
| Baud | Divisor | Actual baud | Error | Status |
|---|
How does a UART generate the baud?
A UART has no baud-rate oscillator of its own: it divides the peripheral clock. A generator samples each bit several times (oversampling, typically 16× or 8×) and a divisor brings the clock down to the baud: div = f_periph / (oversampling · baud_target). The actual baud uses the integer divisor and the error is (actual − target) / target · 100.
A UART has no baud-rate oscillator of its own: it divides the peripheral clock. A generator samples each bit several times (oversampling, typically 16× or 8×) and a divisor brings the clock down to the baud rate:
Why does the error appear?
The ideal divisor is almost always fractional, but the integer one must be an integer: rounding it, the actual baud departs from the target. At 16 MHz and 115200 baud with 16× oversampling the ideal divisor is ~8.68, rounded to 9 it gives 111111 baud, i.e. −3.5% — enough to drop frames.
The ideal divisor is almost always fractional, but the integer one must be... an integer. Rounding it, the actual baud departs from the target. At 16 MHz and 115200 baud with 16× oversampling the ideal divisor is ~8.68: rounded to 9 it gives 111111 baud, i.e. −3.5% — enough to drop frames.
The ±2–3% threshold, and where it comes from
A UART frame is start + 8 data + stop = 10 bits. The receiver samples each bit at its centre, re-calibrating on the start edge; the clock error builds up bit after bit across the frame. Requiring the last bit’s sample to stay inside its window gives the combined budget: (0.5 − 2/S)/(n − 0.5), that is 3.95% for 8N1 at 16× with majority decision. That budget covers BOTH ends together, clock tolerance included: the 2–3% below is how much of it can go to one end alone.
16× vs 8× oversampling
At 16× each bit is sampled over 16 "ticks" and the decision is taken by majority around the centre: more robustness to noise and jitter. At 8× the divisor can halve, so higher bauds are reached with the same clock, but with half the sampling margin. Many MCUs use 16× by default and 8× only for the highest bauds.
What is the fractional divisor?
Many peripherals (for example the STM32 USART) represent the divisor as an integer mantissa plus a 4-bit fraction, in steps of 1/16. Quantizing the fractional part to 1/16 collapses the error: in the 16 MHz/115200 case it drops from −3.5% to under 0.1%. It is the most effective way to “clean up” a baud that would otherwise fail.
Many peripherals (e.g. STM32 USART) represent the divisor as an integer mantissa plus a 4-bit fraction (steps of 1/16). Quantizing the fractional part to 1/16 collapses the error: in the 16 MHz/115200 case it drops from −3.5% to under 0.1%. It is the most effective way to "clean up" a baud that would otherwise fail.
Choosing the right clock
The "magic" clocks for serial are multiples of the baud times the oversampling: at 16× a clock like 14.7456 MHz gives zero error across the whole 9600–921600 family, because 14.7456e6 / 16 = exactly 921600. That is why those odd-looking crystals exist. If the clock is constrained elsewhere, the fractional divisor is the cure.
What are the tool’s limitations?
The fractional quantization used here is 1/16 (4 bits), the most common case; some peripherals have different resolution or constraints. The tool considers only the baud-generator error: it does not model the source-clock tolerance (crystal/PLL) nor jitter, which eat into the same ±2–3% budget. Demonstrative tool: real configuration relies on the UART reference manual and the peripheral registers.
- The fractional quantization used here is 1/16 (4 bits), the most common case; some peripherals have different resolution or constraints (e.g. the least-significant fraction bit in 8× mode).
- It considers only the baud-generator error: it does not model the source-clock tolerance (crystal/PLL) nor jitter, which eat into the same ±2–3% budget.
- Demonstrative tool: real configuration relies on the UART reference manual and the peripheral registers.