# ADC/DAC: resolution, LSB and SNR > The figures of an ADC/DAC converter: quantization and the LSB, the ideal SNR of 6.02·N+1.76 dB, SINAD and ENOB as usable resolution, dynamic range and Nyquist. Published: 2026-06-24 Updated: 2026-08-25 Practice: elettronica Standard: ADC/DAC: resolution, LSB and SNR Page: --- An analog-to-digital (ADC) or digital-to-analog (DAC) converter is described by a handful of figures that are easily confused: resolution, SNR, dynamic range, ENOB. This tool computes them from resolution, reference and sample rate; this page explains where they come from and which one to actually watch. ## Quantization and the LSB An N-bit converter splits the full-scale input range V_ref into 2ᴺ equal steps. The smallest step is the **Least Significant Bit (LSB)**: the smallest voltage change the converter can resolve. It is the grid step onto which every sample is rounded. $$ \text{LSB}=\dfrac{V_{ref}}{2^N} $$ Each extra bit halves the LSB: at the same V_ref, going from 12 to 16 bits shrinks it 16×. A 16-bit ADC with V_ref = 3.3 V has an LSB of about 50 µV — below that level you need clean references and a low noise floor, otherwise the last bits carry no information. ## Ideal SNR: where 6.02·N + 1.76 comes from Rounding a continuous signal to the grid introduces a **quantization error**. If the signal is "lively enough" relative to the LSB, this error is well modelled as **white noise uniform** over ±½ LSB. The variance (power) of a uniform distribution of width LSB is: $$ P_q=\dfrac{\text{LSB}^2}{12} $$ A full-scale sine (peak amplitude V_ref/2) has power P_s = (V_ref/2)²/2. The ratio of the two powers, in dB, is the **ideal SNR**: $$ \text{SNR}=10\log_{10}\!\dfrac{P_s}{P_q}=6.02\,N+1.76\ \text{[dB]} $$ The two terms have a precise meaning: - **6.02 dB/bit** = 20·log₁₀(2): each added bit doubles the number of levels and improves the SNR by about 6 dB. - **+1.76 dB** = 10·log₁₀(1.5): the shape ratio between a full-scale sine and uniform noise. It is a **theoretical ceiling**: no real converter beats it. Known datasheet values: an ideal 12-bit ADC has SNR = 74.0 dB, a 16-bit one = 98.1 dB. ### Typical resolutions compared (V_ref = 3.3 V) | N bits | LSB | ideal SNR | |---|---|---| | 8 | 12.9 mV | 49.9 dB | | 12 | 806 µV | 74.0 dB | | 16 | 50.4 µV | 98.1 dB | | 24 | 197 nV | 146.2 dB | Every 4 bits the ideal SNR rises by ~24 dB and the LSB shrinks 16-fold. The LSB column explains why beyond 16–18 bits the real limit is set by reference and analog front-end noise, not quantization. ## Dynamic range For an **ideal** converter, limited only by quantization noise, the **dynamic range** (ratio of the largest representable signal to the noise floor) numerically equals the full-scale SNR. In real devices the two diverge: distortion and spurious tones lower the SNR but not necessarily the dynamic range measured with a small signal. Here we model the ideal case, so dynamic range = ideal SNR. ## ENOB and SINAD A real converter does not reach its theoretical SNR: thermal noise, clock **jitter**, non-linearity (INL/DNL) and harmonic distortion erode it. The representative measurement is the **SINAD** (Signal-to-Noise-And-Distortion), whose denominator includes not just noise but all harmonics and spurs. Inverting the ideal-SNR formula and substituting the measured SINAD yields the **effective number of bits**, the **ENOB**: $$ \text{ENOB}=\dfrac{\text{SINAD}-1.76}{6.02} $$ A "16-bit" ADC with a 90 dB SINAD has an ENOB of about **14.7 bits**: the last bits are noise, not information. That is why ENOB — not the nominal resolution — is the figure of merit by which converters are really compared. The difference N − ENOB tells how many bits are "lost" relative to the data sheet. ## Aperture jitter, the limit resolution does not tell you about Among the factors that erode real SNR, **aperture jitter** — the uncertainty in the instant the sampler closes — deserves a place of its own, because it does not depend on the converter but on the clock, and because its law is surprisingly severe. Sampling a moment too early or too late produces an amplitude error equal to the signal's slope times the timing error; on a sinusoid of frequency f_in with rms jitter t_j the resulting signal-to-noise ratio is $$ \text{SNR}_{jitter} = -20\log_{10}\!\left(2\pi f_{in} t_j\right) $$ and it contains no N. **It does not depend on resolution**: it is a ceiling the clock imposes on any converter. Since f_in enters linearly, the ceiling falls **20 dB per decade** of input frequency: | Jitter | 1 kHz | 10 kHz | 100 kHz | 1 MHz | 10 MHz | 100 MHz | |---|---|---|---|---|---|---| | 1 ps | 164 dB | 144 dB | 124 dB | 104 dB | 84 dB | 64 dB | | 10 ps | 144 dB | 124 dB | 104 dB | 84 dB | 64 dB | 44 dB | | 100 ps | 124 dB | 104 dB | 84 dB | 64 dB | 44 dB | 24 dB | | 1 ns | 104 dB | 84 dB | 64 dB | 44 dB | 24 dB | 4 dB | **Figura:** Chart of the jitter SNR ceiling against input frequency SNR ceiling imposed by aperture jitter as a function of input signal frequency. Each line is one jitter value and falls 20 dB per decade; the horizontal lines are the quantisation SNR at 12, 16 and 24 bits. Where a line passes below a level, the clock sets the limit, not the bits. The chart reads directly: wherever your jitter line passes **below** the horizontal line of your resolution, the extra bits buy nothing. A 100 ps clock — not a bad clock, for many digital systems — caps you at 64 dB at 1 MHz: less than an 11-bit ADC would give. ### How much jitter you can afford Inverting the formula gives the jitter at which clock noise equals quantisation noise, that is the threshold beyond which the converter starts being clock-limited: | Resolution | Quantisation SNR | at 100 kHz | at 1 MHz | at 10 MHz | |---|---|---|---|---| | 12 bit | 74.0 dB | 317.6 ps | 31.8 ps | 3.2 ps | | 14 bit | 86.0 dB | 79.8 ps | 8.0 ps | 0.8 ps | | 16 bit | 98.1 dB | 19.8 ps | 2.0 ps | 0.2 ps | | 18 bit | 110.1 dB | 5.0 ps | 0.5 ps | 50 fs | | 24 bit | 146.2 dB | 78 fs | 8 fs | 1 fs | The 10 MHz column is why 18- and 24-bit converters live at low frequency: demanding fifty femtoseconds of jitter, or worse one, is not a matter of budget but of the physics of the generator and the clock path. A 24-bit part is a DC-instrumentation and audio component, not an RF one — and the formula says so before any data sheet does. When the two contributions are comparable they add in power. On a 16-bit ADC with a 10 ps clock: | f_in | Jitter SNR | Total SNR | ENOB | |---|---|---|---| | 10 kHz | 124.0 dB | 98.1 dB | 16.0 bit | | 100 kHz | 104.0 dB | 97.1 dB | 15.8 bit | | 1 MHz | 84.0 dB | 83.9 dB | 13.6 bit | | 10 MHz | 64.0 dB | 64.0 dB | 10.3 bit | At 10 kHz jitter is irrelevant and ENOB stays at 16.0. At 1 MHz it has already eaten **2.4 bits**, and at 10 MHz the converter performs like a 10-bit part. None of these figures depends on the quality of the silicon. ## Oversampling and the real signal Two practical corrections to the theoretical ceiling, pulling in opposite directions. ### How many bits oversampling buys Sampling faster than necessary does not reduce total quantisation noise, it **spreads** it over a wider band: filtering afterwards to the useful band throws the out-of-band part away. The gain is 10·log₁₀(OSR), that is **3 dB — half a bit — per doubling**: | OSR | SNR gain | Equivalent bits | |---|---|---| | 2× | +3.0 dB | +0.5 | | 4× | +6.0 dB | +1.0 | | 16× | +12.0 dB | +2.0 | | 64× | +18.1 dB | +3.0 | | 256× | +24.1 dB | +4.0 | | 1024× | +30.1 dB | +5.0 | Four free bits cost a factor of 256 on the sampling rate: a good bargain in the audio band, untenable at high frequencies. What makes it practical is the **noise shaping** of a sigma-delta modulator, which does not merely spread the noise but pushes it out of band: a first-order modulator gains 9 dB per OSR doubling (1.5 bits), a second-order one 15 dB (2.5 bits), a third-order one 21 dB (3.5 bits). It is why a 1-bit sigma-delta at OSR 64 and second order comfortably beats a 16-bit SAR over the same band. ### And if the signal is not full scale The 6.02·N + 1.76 holds for a sinusoid using **all** of the scale. Every decibel of headroom left at the top is a decibel of SNR lost, one for one. On a 16-bit ADC: | Signal level | SNR | ENOB | |---|---|---| | +0 dBFS | 98.1 dB | 16.0 bit | | -6 dBFS | 92.1 dB | 15.0 bit | | -12 dBFS | 86.1 dB | 14.0 bit | | -20 dBFS | 78.1 dB | 12.7 bit | | -40 dBFS | 58.1 dB | 9.4 bit | | -60 dBFS | 38.1 dB | 6.0 bit | Twenty decibels of headroom — a prudent and very common choice to never clip — cost **3.3 bits**: a 16-bit part used at −20 dBFS performs like a 12.7-bit one at full scale. It is the most underrated trade-off in designing an acquisition chain, and it explains why the analogue front-end's gain matters as much as the choice of converter. ## Nyquist and aliasing Sampling at rate f_s, only components below **half** of f_s — the **Nyquist frequency** — are represented without ambiguity: $$ f_{Nyq}=\dfrac{f_s}{2} $$ Any component — useful signal or noise — above Nyquist **folds back** (aliases) into the useful band, where it becomes indistinguishable from a legitimate frequency. That is why an **anti-aliasing filter** always precedes an ADC, attenuating everything above Nyquist before sampling, and oversampling converters use a very high f_s to push the quantization noise out of band. ## Limitations - **Ideal-converter** model: uniform quantization noise only, no distortion, INL/DNL or jitter. The computed SNR is the theoretical ceiling, not the real performance. - ENOB requires a **measured SINAD** on the device: without that figure the tool does not estimate it. - **Full-scale sine** test signal: with smaller or non-sinusoidal signals the numbers change. - Demonstrative tool — it does not replace the characterization of a real converter. ## References - **ADC/DAC vendor application notes** on the relationship between resolution, SNR, SINAD and ENOB and on converter measurement (IEEE Std 1241 definitions). - **Related tool** — the [ADC/DAC Resolution & SNR calculator](/en/tools/adc-dac-snr/) puts this page into practice: enter N, V_ref and f_s and read the LSB, ideal SNR, dynamic range and Nyquist; add a measured SNR/SINAD and get the ENOB.